Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage Vt in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al. “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1074, July 1992, have shown that to reduce short-channel effects for sub-0.05 μm MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that the double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of prior art double-gated MOSFETs consists of a very thin insulating layer for the channel, with two gates, one on each side of the channel. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
In the prior art, SOI wafers can be formed using a so-called ‘SMART’ cut process. Although SMART cutting can be used in forming a thick buried oxide region, problems arise when SMART cutting is employed in forming a thin buried oxide region (30–100 Å). The reason that SMART cut technology cannot be used in fabricating SOI wafers having thin buried oxide regions is that SMART cut technology relies on the implantation of hydrogen ions in a Si wafer to form a uniform cut upon annealing the wafer at elevated temperatures.
To date, there are no adequate means for preparing the substrates required to fabricate double-gated MOSFET structures. The required substrates needed are mainly SOI wafers having a BOX region on the order of from about 30 to about 100 Å. Since the BOX region in these substrates will act as a backgate dielectric in a double-gated MOSFET structure, a gate oxide quality BOX region is required. Hence, there is continued need for developing a method of preparing SOI wafers having a gate-quality, thin BOX region.